XC4000 MODULAR COUNTERS

DISCLAIMER
This information is provided strictly "as-is", and the author accepts no liability of any kind for events which may result from its use. No warranty of any kind is made regarding performance, freedom from faults, etc.

The Xilinx XC4000 series FPGAs include an in-built carry-chain mechanism, which facilitates building efficient counters. To utilise this requires that the counter cells be properly aligned on the die. The standard library counters do not utilise this feature, and compile into "conventional" counter designs, which are inefficient as compared to those based on the dedicated logic. This page describes a set of cascadable blocks which build counters of arbitrary length, employing the fast-carry logic.
The circuits were built as ViewLogic® schematics: these can be downloaded as

The schematics can also be retrieved in PDF:

The counter library comprises 4 principal modules, for building binary counters of arbitrary length, in 2-bit increments. Each increment requires one additional CLB.
The basic counter is parallel loadable, and has a count-enable input. 2 variants exist (implemented by changing the LS 2 bits). The first uses slightly more circuitry, but offers a second Enable input, which is overruled by the Load input. The second is smaller, but has only 1 Enable input, which overrules everything.

The 4 major modules are (click to view the schematic):

CT_LC	1st 2 bits of full-function counter
CT_CL	1st 2 bits of reduced-function counter
CT_2	2 further counter bits
CT_TC	carry-out (all ones) output (optional)

All counters feature a master (Parallel) enable, CEP. This disables all functions when low. The CT_LC base block provides a secondary (CES) enable, which only inhibits counting. The first 3 modules each include 2 bits of the counter: these are implemented in a common sub-module, CC.

All counters are built by taking CT_LC or CT_CL (as desired) for the LS 2 bits, then as many stages of CT_2 as required for the remaining bits. If the TC output is required (all 1's), place a CT_TC stage at the end. The required blocks are concatenated directly, in a vertical column, with LS bits at the bottom. All inter-stage connections abut directly.

All inputs & outputs are active high, except the Clock, whose polarity is programmable. Note that the CPOL input (which sets the clock polarity) must be hardwired to GND or VCC as required, as it is actually eliminated by the logic-reduction phase of the design toolset.

The functionality of these 4 modules is summarised below:

CT_LC

This provides the full (dual enable) count function.

INPUTS		OUTPUTS
Signal	Significance	Signal	Significance
CPOLI	Clock polarity: HI for rising edge, LO for falling edge	Q0,1	Parallel data out
CES	Secondary count enable	CPOLO	Clock polarity out (connect ONLY to next stage)
LD	Parallel load (dominates CES)	CO	Carry out (MUST connect only to following CIN)
CEP	Primary enable parallel (dominates everything)
CK	Clock
D0,1	Parallel data in

OPERATION (when clocked)
CES	LD	CEP	Q0,1
X	X	L	No change
X	H	H	D0,1
L	L	H	No change
H	L	H	Increment

CT_CL

This provides the reduced (single enable) count function.

INPUTS		OUTPUTS
Signal	Significance	Signal	Significance
CPOLI	Clock polarity: HI for rising edge, LO for falling edge	Q0,1	Parallel data out
CEP	Primary enable parallel (dominates everything)	CPOLO	Clock polarity out (connect ONLY to next stage)
LD	Parallel load	CO	Carry out (MUST connect only to following CIN)
CK	Clock
D0,1	Parallel data in

OPERATION (when clocked)
LD	CEP	Q0,1
X	L	No change
H	H	D0,1
L	H	Increment

CT_2

This provides an additional 2 bits of count. Cascade as many as required.

INPUTS		OUTPUTS
Signal	Significance	Signal	Significance
CPOLI	Clock polarity: HI for rising edge, LO for falling edge	Q0,1	Parallel data out
CEP	Primary enable parallel (dominates everything)	CPOLO	Clock polarity out (connect ONLY to next stage)
LD	Parallel load	CO	Carry out (MUST connect only to following CIN)
CK	Clock
D0,1	Parallel data in
CIN	Carry in (MUST connect only to preceding COUT)

OPERATION (when clocked)
LD	CEP	Q0,1
X	L	No change
H	H	D0,1
L	H	Increment

CT_TC

This is a dummy module, which is connected above the MS bit, to provide a TC output. If TC is not required, this module is not necessary.

INPUTS		OUTPUTS
Signal	Significance	Signal	Significance
CIN	Carry in (MUST connect only to preceding COUT)	TC	Terminal carry (ie all counter bits =1)

FPGA CELL PLACEMENT

For these counters to be properly compiled, their cells must be assigned to correct FPGA cell locations. This is done by attaching a relative location (RLOC) attribute to each cell. The cells are assembled in a single column, with the most significant bit (carry-out, if used) at the top.
Label each cell in sequence (DOWN the column):

RLOC=R0C0
RLOC=R1C0
etc.

This does not bind the counter to an exact die location, but constrains the relative placement of cells within a given counter.
Design rules:

The cells will abut in a vertical column, LS at the bottom.
Each counter must be put in a separate symbol, to avoid clashes between the RLOC statements.
CPOL must be hardwired to Vcc or GND, ie programmable polarity is not allowed.

An example may be seen in the address counter used in the TAP Loader design.

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