NOTES: where possible I'll have references to Tricep. I'll also have a section talking about how Tricep uses all the features of the bus and why the design needs the bus. This will be at the end or perhaps a sidebar. -bjg- The IEEE-696/S-100 BUS Iî 197µ á smalì companù nameä MITÓ iî Alburqurque¬ N.M® announceä á  producô  iî  Populaò electronicó whicè waó  tï  establisè  thå beginninç  oæ thå micrï computeò revolution®  Thå producô waó  á kit¬  baseä upoî á 10° piî buó designeä foò easù expansion® MITÓ publisheä  thå specificationó foò thå buó bringinç abouô whaô  ió todaù referrreä tï aó thå firsô "opeî architecture¢ computeò iî á worlä theî dominateä bù proprietarù minicomputeò busses® Thå  Altaiò buó aó iô waó knowî iî thoså dayó sooî becamå adopteä bù severaì entreprenueró whï rallieä arounä thå Homebre÷ Computeò Cluâ iî thå soutè bay®  Worä oæ theså ne÷ anä excitinç additionó foò  thå Altaiò buó spreaä beyonä thå cluâ anä sooî á markeô  waó born®  Companieó sucè aó Imsai¬  Processoò Technology¬  Cromemcï sprouteä  uð  makinç "pluç compatable¢ boardó foò  whaô  no÷  waó beinç  calleä thå "S-10° Bus¢ (á terí usuallù attributeä tï Rogeò Mellen¬ á pricipaì oæ Cromemco). Althougè  thå S-10° buó signaló werå fairlù welì  defineä  (beinç originallù  aî extensioî oæ thå 808° uprocessoò itself© therå waó á  tendancù  oæ  manufactureró tï modifù  thå  meaning/nameó  anä timinç  oæ  somå  oæ  thå  lineó  foò  theiò  owî  designs®  Somå manufactureró  eveî  addeä theiò owî signaló  tï  thå  unassigneä lines®   Bù   197¹  thå  compatabilitù  oæ  productó  froí   onå manufactureò  witè productó oæ otheò manufactureró waó iî seriouó jeopardy. Iî 1979¬ perhapó thousandó oæ designó later¬ somå S-10° designeró decideä  iô  waó timå tï drafô á specificatioî foò  thå  buó  anä presenô  iô  tï thå IEEÅ foò professionaì anä publiã  inspection® Georgå  Morrow¬  oæ Morro÷ Designó waó chairmaî oæ  thå  comitteå and¬  alonç witè Howarä Fullmeò (Morro÷ Designs)¬  Kelló Elmquisô (Intersystems© anä Daviä Gustavsoî (Stanforä Lineaò Accelerator), helä  meetingó  witè  memberó oæ thå S-10°  desigî  communitù  tï hammeò  ouô á specificatioî whicè woulä guaranteå á standarä  foò interfacå  anä á futurå growtè patè aó ne÷ microprocessoró becamå available. Afteò manù revisionó anä á changå iî chairmanshið (assumeä bù Soì Libes© thå standarä becamå adopteä bù thå IEEÅ aó thå IEEE-696/S- 10° Standarä iî 1982. Š I. Highlites of the S-100 bus Amonç thå mosô powerfuì featureó oæ thå S-10° bõs arå it'ó supporô oæ botè ¸ biô anä 1¶ biô boardó anä itó fulì DMÁ arbitration. Unlikå otheò defactï standarä busseó (Apple¬  IBÍ PC¬ STD© thå S- 10°  buó haó dedicateä lineó allowinç accesó tï botè 1¶ biô anä ¸ biô  devices®  Thå  buó masteò assertó sXTRÑ aô thå starô  oæ  á cyclå  anä checkó foò SIXTÎ froí thå slavå device®  Iæ thå slavå doesn'ô respond¬  thå accesó ió performeä aó aî ¸ biô  operation® Thió  noô  onlù allowó supporô oæ oldeò ¸ biô S-10° productó  buô allowó  thå  designeò tï optimizå thå cost/performancå  ratiï  bù usinç thå appropriatå datá transfeò sizå tï meeô thå application. Foò instance¬  iî thå Morro÷ Tricep¬  alì CPÕ accesó tï memorù ió performeä  usinç 1¶ biô transferó whereaó alì DMÁ  I/Ï  functionó arå  performeä  iî  ¸  biô  mode®  Thå  systeí  memorù  respondó appropriately tï thå requesting master device. Direcô  Memorù  Accesó  (DMA© ió thå processó bù whicè  á  devicå temporarilù  accesseó thå buó foò á particulaò procesó  anä  theî relinquisheó control® Tï morå clearlù describå thå procesó aó iô applieó  tï  thå bus¬  thå committeå memberó labeleä thå  procesó Temporarù Masteò Accesó (TMA)® Althougè TMÁ ió noô uniquå tï thå S-10° bus, TMA with arbitration is unique. Arbitratioî  oî  thå  S-10° buó allowó uð tï 1¶  TMÁ  deviceó  tï sharå  thå resourceó oî thå bus®  Iæ morå thaî onå  TMÁ  deviceó requesô  thå  buó  simaltaneously¬  thå devicå witè  thå  highesô prioritù  wilì gaiî accesó whilå thå devicå witè lesseò  prioritù musô suspenä itó requesô untiì iô haó priority® Slo÷ deviceó caî theî  bå  intermixeä witè fasô deviceó withouô  thå  overheaä  oæ softwarå scheduling. Thå  Morro÷  Triceð foò instancå assignó highesô prioritù tï  thå DMÁ  harä  disë controlleò becauså iô ió perhapó  thå  mosô  timå dependanô  elemenô  oæ  á Uniø systeí anä ió shareä  bù  alì  thå processes®  Terminaì I/Ï ió giveî á verù lo÷ DMÁ prioritù sincå itó functionó arå faò lesó timå criticaì anä arå useò dependant. c) Ideal slave environment 1) slaves can be either TMA devices with local CPU and resources or non TMA devices Morrow calls "smart memory devices". Smart memory devices are usually dual ported memory, accessable on one side by all kinds of bus masters and on the other side by the local processor. This local processor makes the device a "smart memory". d) Low cost (for a IEEE bus) 1) The boards are relatively small in comparison to minicomputers but allow an average of 90 I.C.s on a 4 layer board. 2) Onboard regulation of power reduces stringent power supply requirements requiring only a three voltage filtered supply. Š 3) Form factor allows small package (cite Cromemco 5 slot unit and Zenith Z-100) 4© Widå availabilitù oæ inexpensivå prototypå anä buó debugging boardó foò systemó intergrators to add their own boards or devices. e) Seperate I/O and Memory space 1) allows full use of the 16 Mbyte memory space while still providing for 65536 I/O devices. I/O devices need not be in the system memory map (unless desired) f) Many operating systems, languages supported 1) CP/M, (8080, 8086, 68000 versions) M/PM, CP/M Plus, Unix, Zenix, Genix, Idris, Regulus, Oasis, MS-DOS, Forth, UCSD P system, Turbodos (both 8 and 16 bit), 2) All the above operating systems virtually assure that a wide variety of language compilers and interpreters are available. It also assures availability of cross compilers, linkers and assemblers are available. g) Open and well defined 1© unlikå proprietarù buseó oæ manufactureró whicè havå yeô tï establisè themselveó aó á defactï standard¬ thå S-10° buó provideó a wide open architecture. It is defined by an IEEE standard and cannot change without formal proceedings. (Cite the problems with the PC bus being 8 bit data width only and the problems faced by manufacturers trying to get true 16 bit devices to work correctly). h) Copious amounts of hardware 1) graphics (low, medioum, high and very high resolutions) 2) emulators, analyzers, software developement products 3) A/D and D/A (both low and high speed devices) 4) speech 5) "real world" controller and monitoring devices 6) controllers (SASI, SCSI, SMD, ST-506, Quik 02, IEEE-488, 9 TRACK TAPE, 8 and 5 inch Floppy) 7) memory 64K low power CMOS to 2 Mbyte DRAM with ECC i) Copious amounts of CPUs 1) 8080, z80, 8085, 8088, 8086, 80186, 80286, 6800, 6809, 68000, 68010, 9900, NS16032, j) Networks 1) Ethernet, Northnet, Cnet, Arcnet k) 10 available interrupt lines 1) allow for an interrupt rich implementation for environments such as Unix. II. Advantages of an IEEE standard bus a) cross manufacturer repsonsibility to adhere to standards Šb) no bugs to come out of the woodwork during design or integration phases as a result of poorly defined or inadequately spec'd bus c) upgradablå  bù  committee concensuó  ratheò  thaî aô thå whií  oæ  á  singlå manufacturer (IBM with the 8 bit PC bus). e) wide supplier sources for products (card cages, power supplies, boards, chassis etc.) III. Uses of the bus (not in any order) a) Graphics systems b) Test equipment c) Dedicated Controllers and monitors d) Small business systems (single user very high performance) e) Multi-useò computeò systemó (Unix, Turbodos¬ Oasis¬ MP/Í ) f) Networked multiuser systems g) Software and Hardware Developement systems h) Scientific capture systems IV. Problems a) 24 bit address restriction 1) this may be solved by use of the RFU (reserved for future use) lines on the bus and should be explored at which point 32 bit address space is required. b) 16 bit data path 1) this can be solved by making all TMA or MASTER devices perform two 16 bit fetches similar to how current 16 bit devices work with 8 bit slaves. c) synchronous 1) the bus, since it originated with the 8080, was designed for synchronous devices. This is not optimum for certain high speed, high performance designs. Again an RFU line could be used to add this capability. d) unregulated supply 1) This makes power supplies simple but limits board space due to on board regulators. 2) Cooling requirements for the onboard regulators is trickier. NOTE: This could be solved if the standard could include a provision to run boards with regulated supplies. (Intersystems has done this already although it is not a standard) V. Single board closed architecture vs. bus oriented open architecture debate a) cost, b) flexability c) change CPU, change computer d) interchangeable parts e) upgradability f) power (AC) Š g) size and weight VI. Tricep and how it uses the S-100 bus to its full potential VII. Summary Bob Groppo Engineering Product Manager Morrow Designs San Leandro, Ca.