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Z80 Flag Affection

This document is an adaption of the flags page on Mark Rison's Z80 Page.
This page is made by Sean Young

The flag register has the following structure:
Bit 7 6 5 4 3 2 1 0
Flag S Z F5 H F3 P/V N C
The flags are set according to the result of the last instruction. The standard behaviour is:

S - Sign flag
Set if the 2-complement value is negative (copy of MSB)
Z - Zero flag
Set if the value is zero
F5 - undocumented flag
Copy of bit 5
H - Half Carry
Carry from bit 3 to bit 4
F3 - undocumented flag
Copy of bit 3
P/V - Parity or Overflow
Parity set if even number of bits set
Overflow set if the 2-complement result does not fit in the register
N - Subtract
Set if the last operation was a subtraction
C - Carry
Set if the result did not fit in the register
The following table contains all the instructions that affect the F register. 
? indicates the effect is undefined.

* indicates the effect is non-standard (see the notes).

0 indicates the flag is reset.

1 indicates the flag is set.

- indicates the flag is not affected.

S,Z,5,H,3,P,V,N,C indicate the flag is set as above.



r refers to any 8-bit quantity appropriate for that instruction.

s refers to any 16-bit quantity appropriate for that instruction.



Instruction           Flags     Notes

===========           =====     =====



ADD/ADC/SUB/SBC       SZ5H3VNC  

CP r                  SZ*H*VNC  CP is just SUB with the result thrown away

				F5 and F3 are copied from the operand, not the result



INC/DEC r             SZ5H3VN-



16 bit additions are done in two steps: 

First the two lower bytes are added, the two higher bytes.



ADD s                 --***-0C  F5,H,F3 from higher bytes addition

ADC/SBC s             SZ***VNC  F5,H,F3 from higher bytes addition



AND r                 SZ513P00

OR/XOR r              SZ503P00



RLCA/RLA/RRCA/RRA     --503-0C

RLC/RL/RRC/RR r       SZ503P0C

SLA/SLL/SRA/SRL r     SZ503P0C  SLL is like SLA except b0 gets set

RRD/RLD               SZ503P0-  Flags set on result in A



BIT n,r               *Z513*0-  PV as Z, S set only if n=7 and b7 of r set

				Behaves much like AND r,2^n



CCF                   --***-0*  C=1-C, H as old C

				F5, F3 from A register



SCF                   --*0*-01	F5, F3 from A register

CPL                   --*1*-1-	F5, F3 from A register

NEG                   SZ5H3V1C  A=0-A (Zaks gets C wrong)

DAA                   SZ5*3P-*  H from internal correction, C for cascade BCD



LD A,R/LD A,I         SZ503*0-  PV as IFF2 [yaze doesn't affect F?]



LDI/LDIR/LDD/LDIR     --*0**0-  PV set if BC not 0

				F5 is bit 1 of (transferred byte + A)

				F3 is bit 3 of (transferred byte + A)



CPI/CPIR/CPD/CPDR     SZ*H**1-  PV set if BC not 0

                                S,Z,H from (A - (HL) ) as in CP (HL)

				F3 is bit 3 of (A - (HL) - H), H as in F after instruction

				F5 is bit 1 of (A - (HL) - H), H as in F after instruction



IN r,(C)              SZ503P0-	Also true for IN F,(C)



INI/INIR/IND/INDR     SZ5?3???  Flags affected as in DEC B

OUTI/OTIR/OUTD/OTDR   SZ5?3???  Flags affected as in DEC B



All others            --------  Except for POP AF and EX AF,AF', of course...
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