-  /ex /id /sh /ish/
-  /mir/ex /bm /bf /a8 /ac /cpu/a16/rsb/jp /cal/ret/pio/
-  /ra /rr /rr2/imm/ihl/iss/abs/idx/ptn/ptc/hl /ss /qq /xy /pp /dim/dab/axy/p0 /rel/stk/bit/cc /cc2/ahl/im4/

	*********************************************************
	*							*
	*	 ZEM  Z80  EMULATOR  DECODER  DATA  FILE	*
	*							*
	*	 First 3 lines are literals strings.		*
	*	 There are notes on the format at the		*
	*	 end of this file.				*
	*							*
	*	     ZEM  Z80 Emulator and Monitor		*
	*	      Version 1.03   22 June 1986		*
	*							*
	*	     (C) 1986 by P. G. Kenny			*
	*			 27 Colwyn Road			*
	*			 Northampton			*
	*							*
	*  Permission is hereby granted for all non-commercial	*
	*  reproduction and distribution of this material	*
	*  provided this notice is included.			*
	*							*
	*********************************************************


 ** 8-bit load group **

-   01xxxxxx  1  4 -    rr > <rr2  ld
-   01xxx110* 1  7 -    rr > <ihl  ld
-   01110xxx* 1  7 -    ihl> <rr2  ld
-   01110110?
id  01xxx110  3 19 -    rr > <idx  ld
id  01110xxx* 3 19 -    idx> <rr2  ld
id  01110110?
-   00xxx110  2  7 -    rr > <imm  ld
-   00110110* 2 10 -    ihl> <imm  ld
id  00110110  4 19 -    idx> <im4  ld
-   000x1010  1  7 -    ra > <iss  ld
-   00111010  3 13 -    ra > <abs  ld
-   000x0010  1  7 -    iss> <ra   ld
-   00110010  3 13 -    abs> <ra   ld

ex  01010111  2  9 mir  -     -    ld   a, i
ex  01011111  2  9 mir  -     -    ld   a, r
ex  01000111  2  9 mir  -     ra   ld   i
ex  01001111  2  9 mir  -     ra   ld   r

 ** 16-bit load group **

-   00xx0001  3 10 -    ss > <dim  ld
id  00100001  4 14 -    xy > <dim  ld
-   00101010  3 16 -    hl > <dab  ld
ex  01xx1011  4 20 -    ss > <dab  ld
id  00101010  4 20 -    xy > <dab  ld
-   00100010  3 16 -    dab> <hl   ld
ex  01xx0011  4 20 -    dab> <ss   ld
id  00100010  4 20 -    dab> <xy   ld
-   11111001  1  6 -    ss > <hl   ld
id  11111001  2 10 -    ss > <xy   ld

-   11xx0101  1 11 -   <qq    stk> push
id  11100101  2 15 -   <xy    stk> push
-   11xx0001  1 10 -    qq > <stk  pop
id  11100001  2 14 -    xy > <stk  pop

 ** exchange group **

-   11101011  1  4 ex   -     hl   ex   de
-   00001000  1  4 ex   -     -    ex   af, af'
-   11011001  1  4 ex   -     -    exx
-   11100011  1 19 ex   -    <hl > ex   (sp)
id  11100011  2 23 ex   -    <xy > ex   (sp)

 ** block move group **

ex  10100000  2 16 bm   -     -    ldi
ex  10110000  2 16 bm   -     -    ldir
ex  10101000  2 16 bm   -     -    ldd
ex  10111000  2 16 bm   -     -    lddr

 ** block find group **

ex  10100001  2 16 bf   -     -    cpi
ex  10110001  2 16 bf   -     -    cpir
ex  10101001  2 16 bf   -     -    cpd
ex  10111001  2 16 bf   -     -    cpdr

 ** 8 bit arithmetic group **

-   10000xxx  1  4 a8   ra   <rr2  add
-   10000110* 1  7 a8   ra   <ihl  add
id  10000110  3 19 a8   ra   <idx  add
-   11000110  2  7 a8   ra   <imm  add

-   10001xxx  1  4 a8   ra   <rr2  adc
-   10001110* 1  7 a8   ra   <ihl  adc
id  10001110  3 19 a8   ra   <idx  adc
-   11001110  2  7 a8   ra   <imm  adc

-   10010xxx  1  4 a8  <rr2   -    sub
-   10010110* 1  7 a8  <ihl   -    sub
id  10010110  3 19 a8  <idx   -    sub
-   11010110  2  7 a8  <imm   -    sub

-   10011xxx  1  4 a8   ra   <rr2  sbc
-   10011110* 1  7 a8   ra   <ihl  sbc
id  10011110  3 19 a8   ra   <idx  sbc
-   11011110  2  7 a8   ra   <imm  sbc

-   10100xxx  1  4 a8  <rr2   -    and
-   10100110* 1  7 a8  <ihl   -    and
id  10100110  3 19 a8  <idx   -    and
-   11100110  2  7 a8  <imm   -    and

-   10101xxx  1  4 a8  <rr2   -    xor
-   10101110* 1  7 a8  <ihl   -    xor
id  10101110  3 19 a8  <idx   -    xor
-   11101110  2  7 a8  <imm   -    xor

-   10110xxx  1  4 a8  <rr2   -    or
-   10110110* 1  7 a8  <ihl   -    or
id  10110110  3 19 a8  <idx   -    or
-   11110110  2  7 a8  <imm   -    or

-   10111xxx  1  4 a8  <rr2   -    cp
-   10111110* 1  7 a8  <ihl   -    cp
id  10111110  3 19 a8  <idx   -    cp
-   11111110  2  7 a8  <imm   -    cp

-   00xxx100  1  4 a8  <rr >  -    inc
-   00110100* 1 11 a8  <ihl>  -    inc
id  00110100  3 23 a8  <idx>  -    inc

-   00xxx101  1  4 a8  <rr >  -    dec
-   00110101* 1 11 a8  <ihl>  -    dec
id  00110101  3 23 a8  <idx>  -    dec

 ** accumulator and flag group **

-   00100111  1  4 ac   -     -    daa
-   00101111  1  4 ac   -     -    cpl
ex  01000100  2  8 ac   -     -    neg
-   00111111  1  4 ac   -     -    ccf
-   00110111  1  4 ac   -     -    scf

 ** miscellaneous cpu control group **

-   00000000  1  4 cpu  -     -    nop
-   01110110  1  4 cpu  -     -    halt
-   11110011  1  4 cpu  -     -    di
-   11111011  1  4 cpu  -     -    ei
ex  01000110  2  8 cpu  -     -    im   0
ex  01010110  2  8 cpu  -     -    im   1
ex  01011110  2  8 cpu  -     -    im   2

 ** 16 bit arithmetic group **

-   00xx1001  1 11 a16  hl > <ss   add
ex  01xx1010  2 15 a16  hl > <ss   adc
ex  01xx0010  2 15 a16  hl > <ss   sbc
id  00xx1001  2 15 a16  xy > <pp   add

-   00xx0011  1  6 a16 <ss >  -    inc
id  00100011  2 10 a16 <xy >  -    inc
-   00xx1011  1  6 a16 <ss >  -    dec
id  00101011  2 10 a16 <xy >  -    dec

 ** rotate and shift group **

-   00000111  1  4 ac   -     -    rlca
-   00010111  1  4 ac   -     -    rla
-   00001111  1  4 ac   -     -    rrca
-   00011111  1  4 ac   -     -    rra

sh  00000xxx  2  8 rsb <rr2>  -    rlc
sh  00000110* 2 15 rsb <ihl>  -    rlc
ish 00000110  4 23 rsb <idx>  -    rlc

sh  00010xxx  2  8 rsb <rr2>  -    rl
sh  00010110* 2 15 rsb <ihl>  -    rl
ish 00010110  4 23 rsb <idx>  -    rl

sh  00001xxx  2  8 rsb <rr2>  -    rrc
sh  00001110* 2 15 rsb <ihl>  -    rrc
ish 00001110  4 23 rsb <idx>  -    rrc

sh  00011xxx  2  8 rsb <rr2>  -    rr
sh  00011110* 2 15 rsb <ihl>  -    rr
ish 00011110  4 23 rsb <idx>  -    rr

sh  00100xxx  2  8 rsb <rr2>  -    sla
sh  00100110* 2 15 rsb <ihl>  -    sla
ish 00100110  4 23 rsb <idx>  -    sla

sh  00101xxx  2  8 rsb <rr2>  -    sra
sh  00101110* 2 15 rsb <ihl>  -    sra
ish 00101110  4 23 rsb <idx>  -    sra

sh  00111xxx  2  8 rsb <rr2>  -    srl
sh  00111110* 2 15 rsb <ihl>  -    srl
ish 00111110  4 23 rsb <idx>  -    srl

ex  01101111  2 18 rsb  -     -    rld
ex  01100111  2 18 rsb  -     -    rrd

 ** bit set, reset and test group **

sh  01xxxxxx  2  8 rsb  bit  <rr2  bit
sh  01xxx110* 2 12 rsb  bit  <ihl  bit
ish 01xxx110  4 20 rsb  bit  <idx  bit

sh  11xxxxxx  2  8 rsb  bit  <rr2> set
sh  11xxx110* 2 15 rsb  bit  <ihl> set
ish 11xxx110  4 23 rsb  bit  <idx> set

sh  10xxxxxx  2  8 rsb  bit  <rr2> res
sh  10xxx110* 2 15 rsb  bit  <ihl> res
ish 10xxx110  4 23 rsb  bit  <idx> res

 ** jump group **

-   11000011  3 10 jp  <dim   -    jp
-   11xxx010  3 10 jp   cc   <dim  jp
-   00011000  2 12 jp  <rel   -    jr
-   001xx000  2  7 jp   cc2  <rel  jr
-   11101001  1  4 jp  <ahl   -    jp
id  11101001  2  8 jp  <axy   -    jp
-   00010000  2  8 jp  <rel   -    djnz

 ** call and return group **

-   11001101  3 17 cal <dim   -    call
-   11xxx100  3 10 cal  cc   <dim  call
-   11xxx111  1 11 cal <p0    -    rst

-   11001001  1 10 ret  -     -    ret
-   11xxx000  1  5 ret  cc    -    ret
ex  01001101  2 14 ret  -     -    reti
ex  01000101  2 14 ret  -     -    retn

 ** input and output group **

-   11011011  2 11 -    ra > <ptn  in
ex  01xxx000  2 12 pio  rr > <ptc  in
ex  01110000?
ex  10100010  2 15 pio  -     -    ini
ex  10110010  2 15 pio  -     -    inir
ex  10101010  2 15 pio  -     -    ind
ex  10111010  2 15 pio  -     -    indr

-   11010011  2 11 -    ptn> <ra   out
ex  01xxx001  2 12 -    ptc> <rr   out
ex  01110001?
ex  10100011  2 15 pio  -     -    outi
ex  10110011  2 15 pio  -     -    otir
ex  10101011  2 15 pio  -     -    outd
ex  10111011  2 15 pio  -     -    otdr

	*********************************
	*				*
	*	Notes on format		*
	*				*
	*********************************

 ccc bbbbbbbb$ l tt fff <am1> <am2> mnem
 ^   ^       ^ ^ ^  ^   ^ ^ ^ ^ ^ ^ ^
 |   |       | | |  |   | | | | | | = mnemonic string
 |   |       | | |  |   | | | | | = . post-store flag for op2
 |   |       | | |  |   | | | | = ... address mode literal for op2
 |   |       | | |  |   | | | = ..... pre-load flag for op2
 |   |       | | |  |   | | = ....... post-store flag for op1
 |   |       | | |  |   | = ......... address mode literal for op1
 |   |       | | |  |   = ........... pre-load flag for op1
 |   |       | | |  = ............... function literal
 |   |       | | = .................. time in cycles
 |   |       | = .................... length in bytes
 |   |       = ...................... supression flags
 |   = .............................. bit pattern
 = .................................. class literal (starts in 1st column)

 Notes :
 ~~~~~~~
 A white-space character in the first column indicates a comment line.

 The first 3 lines of the file contain the literal assignments for class,
 function and address mode.

 The bit pattern may contain '0' , '1' or 'x', where 'x' means don't care.

 The optional suppression flags are :
    '*' - ignore double definition error
    '?' - this bit pattern is to be undefined

 The time value is the minimum for the instruction, any extra time needed
 (for example by the JR group) is added when the instruction is executed.


 --------------------------  END OF ZEMDDAT.ASC  -----------------------------
s added when the instruction is executed.


 --------------------------  END OF ZEMDDAT.ASC  ------